The present invention relates generally to memory devices and, more particularly, to a method of programming a threshold changing material of a memory cell to allow for multilevel data storage and associated reading techniques.
The resistance ratio of amorphous and crystalline chalcogenide is typically more than 1000 times. Due to this difference it has been proposed to separate the resistance into several stages and utilize the stages for are multi-level storage. FIG. 1 is a graph illustrating a plot of the resistance versus the current for a multi-level chalcogenide random access memory (RAM). As is illustrated by line 102, the resistance steps up according to each current increment. The resistance of chalcogenide may be tuned, however, one of the shortcomings associated with defining the stages through the resistance is that the resistance difference is difficult to sense because the sensing margin is small for multi-level applications and the sensing time for the high resistance stage will be long. For example, assuming that there are 4 states of resistance and they are 5 k, 50 k, 500 k and 5M Ohm, the current to read a cell is usually 20 μA. If we apply 0.1 V on a cell, and the cell resistance may be 5 k, 50 k, 500 k and 5M, the current read will be 20 μA, 2 μA, 0.2 μA (which can be hardly sensed), and 20 nA (the same order as noise), respectively. That is, it is almost impossible to sense all the states at that level.
In light of the foregoing, there is a need for a multi-level (multiple bits per cell) memory cell structure that includes a feature that is readily sensed for the multiple levels so that the associated states may be easily discerned.